Blocks are grouped together in Model Composer by using a Subsystem. Grouping blocks within a clock domain is no different except that a System Generator token has to be placed in the Subsystem you want to “mark” as a Clock Domain. This is shown in the following figure.
In this figure, a clock domain Subsystem called src_domain has been created and a System Generator token added. Notice that
the clocking tab of the System Generator
token is selected. In this tab, the FPGA clock period has been set to
(1000/368) ns (368 MHz) and the Simulink
system period to 1. This implies that an advance of 1 Simulink second corresponds to (1000/368)
ns of FPGA clock.
Similarly, another group of blocks representing another clock
domain is included in a Subsystem called dest_domain, as shown in the figure below.
In this design, the dest_domain
Subsystem is configured to run at an FPGA clock period of 1000/245 ns (245
MHz). The Simulink system period is set
to 368/245. This is done because the Simulink system period of the src_domain Subsystem is set to 1. Hence, you normalize
with the System period from the src_domain
which is faster.