Packaging the Design for Use in Vivado IP Integrator - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
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2022.1 English

When you complete the verification in Model Composer, you can package the design for use in IP integrator.

Figure 1. Model Composer Verification

The HDL block must first be configured to a Compilation target of IP Catalog (the default generation target). This compilation target will consolidate all hardware source created from Model Composer (RTL + IP + Constraints) into an IP.

The part selected is the same part as that available on the Xilinx Zynq-7000 ZC702 Evaluation Board. In addition, you may also use the Settings button on the System Generator token to change the information that goes along with the IP. In this case, the default values shown below are used.

Figure 2. IP Catalog Settings

When you click the Generate button in System Generator token GUI, RTL+IP+Constraints generation, as well as packaging takes place.