Generating C++ Code - 2022.1 English

The following figure shows the HLS C++ Code output by Model Composer from the Generate command. The C++ code is output either as an intermediate step when generating a packaged IP for System Generator output, or as a specified output to let you optimize the C++ code using directives or pragmas in Vitis HLS.

Figure 1. C++ Output Files

The files generated by Model Composer reflect the contents and hierarchy of the subsystem that was compiled. In this case, the subsystem is the Edge Detection function described in the Model Composer section of the Vitis Model Composer Tutorial (UG1498). The following figure shows the contents of the Edge Detection subsystem.

#include "Edge_Detection.h"
#include "GradMagnitude.h"
#include "SobelFilter.h"

The following shows the generated code for the Edge Detection subsystem. Notice the pragmas added to the function to specify the function protocol and the I/O port protocols for the function signature and return value. The pragmas help direct the solution synthesized by Vitis HLS, and result in higher performance in the implemented RTL.

Edge_Detection(hls::stream< ap_axiu<16, 1, 1, 1> >& Y, 
    hls::stream< ap_axiu<16, 1, 1, 1> >& Y_Out)
{
    #pragma HLS INTERFACE s_axilite port=return
    #pragma HLS INTERFACE axis bundle=image_out port=Y_Out
    #pragma HLS INTERFACE axis bundle=input_vid port=Y
    #pragma HLS dataflow
    uint8_t core_Y[360][640];
    #pragma HLS stream variable=core_Y dim=2 depth=1
    uint8_t core_Cb[360][320];
    #pragma HLS stream variable=core_Cb dim=2 depth=1
    uint8_t core_Cr[360][320];
    #pragma HLS stream variable=core_Cr dim=2 depth=1
    uint8_t core_Y_Out[360][640];
    #pragma HLS stream variable=core_Y_Out dim=2 depth=1
    uint8_t core_Cb_Out[360][320];
    #pragma HLS stream variable=core_Cb_Out dim=2 depth=1
    uint8_t core_Cr_Out[360][320];
    #pragma HLS stream variable=core_Cr_Out dim=2 depth=1
    fourier::AxiVideoStreamAdapter< uint8_t >::readStreamVf0(Y, 
        reinterpret_cast< uint8_t* >(core_Y), reinterpret_cast< uint8_t* >(
        core_Cb), reinterpret_cast< uint8_t* >(core_Cr), 360, 640);
    Edge_Detection_core(core_Y, core_Cb, core_Cr, core_Y_Out, core_Cb_Out, 
        core_Cr_Out);
    fourier::AxiVideoStreamAdapter< uint8_t >::writeStreamVf0(Y_Out, 
        reinterpret_cast< uint8_t* >(core_Y_Out), reinterpret_cast< uint8_t* >(
        core_Cb_Out), reinterpret_cast< uint8_t* >(core_Cr_Out), 360, 640);
}

Finally, notice the run_hls.tcl file that is generated in the output folder. This is a Tcl script that can be used to run Vitis HLS on the generated output files to create a project and solution, synthesize the RTL from the C++ code, and export the design to the Model Composer HDL model. Each Vitis HLS project holds one set of C/C++ code and can contain multiple solutions. Each solution can have different constraints and optimization directives. For more information refer to the Vitis High-Level Synthesis User Guide (UG1399).

vitis_hls -p ./Edge_Detection_proj

This will open the Vitis HLS project in the GUI Mode.