For all HDL blocks in the src_domain, the clocking
is governed by the System Generator token in the src_domain Subsystem.
Similarly for the dest_domain
Subsystem. For the FIFO block, the clocks are derived from its
context in the design. Because the we and din
ports are driven by signals emanating from the src_domain Subsystem, the
wr_clk of the FIFO
is tied to the src_domain
clock. Because the dout,
full, and re ports either drive or
load signals from dest_domain,
the rd_clk of the FIFO is tied
to the dest_domain clock.
Mixing and matching these signals across clock domains or using
any other block (other than FIFO or Dual Port RAM) to cross
clock domains will result in a DRC error.