System-Level Modeling in Model Composer - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

Model Composer allows device-specific hardware designs to be constructed directly in a flexible high-level system modeling environment. In a Model Composer design, signals are not just bits. They can be signed and unsigned fixed-point numbers, and changes to the design automatically translate into appropriate changes in signal types. Blocks are not just stand-ins for hardware. They respond to their surroundings, automatically adjusting the results they produce and the hardware they become.

Model Composer allows designs to be composed from a variety of ingredients. Data flow models, traditional hardware description languages (VHDL and Verilog), and functions derived from the MATLAB programming language, can be used side-by-side, simulated together, and synthesized into working hardware. Model Composer HDL block simulation results are bit and cycle-accurate. This means results seen in simulation exactly match the results that are seen in hardware. Model Composer simulations are considerably faster than those from traditional HDL simulators, and results are easier to analyze.

Model Composer HDL Blocksets Describes how Model Composer's HDL blocks are organized in libraries, and how the blocks can be parameterized and used.
Xilinx Commands that Facilitate Rapid Model Creation and Analysis Introduces Xilinx commands that have been added to the Simulink pop-up menu that facilitate rapid Model Composer model creation and analysis.
Signal Types Describes the data types used by Model Composer and ways in which data types can be automatically assigned by the tool.
Bit-True and Cycle-True Modeling Specifies the relationship between the Simulink-based simulation of a Model Composer model and the behavior of the hardware that can be generated from it.
Timing and Clocking Describes how clocks are implemented in hardware, and how their implementation is controlled inside Model Composer. Explains how Model Composer translates a multirate Simulink model into working clock-synchronous hardware.
Synchronization Mechanisms Describes mechanisms that can be used to synchronize data flow across the data path elements in a high-level Model Composer design, and describes how control path functions can be implemented.
Block Masks and Parameter Passing Explains how parameterized systems and Subsystems are created in Simulink.