Features of the Vivado IDE Example Project - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.1 English

The Vivado® IDE example project (example_dds.xpr) is created to help you jump start your usage of the IP created from Model Composer. This project is configured as follows:

  1. The IP generated from Model Composer is already added to the IP catalog associated with the project and available for the RTL flow as well as the IP integrator-based flow.
  2. The design includes an RTL instantiation of IP called example_dds_0 underneath example_dds_stub that indicates how to instance such an IP in RTL flow.
  3. The design includes a test bench called example_dds_tb that also instances the same IP in RTL flow.
  4. The design includes an example IP integrator diagram with a Zynq®-7000 Subsystem as the part selected in this example is a Zynq®-7000 SoC part. For all other parts, a MicroBlaze-based Subsystem is created.
    Figure 1. IP Integrator Diagram
  5. If the part selected is the same as one of the supported boards, the project is set to the first board encountered with the same part setting.
  6. A wrapper instancing the block design is created and set as Top.
Tip: The interface documentation associated with the IP is accessible through the block GUI. To access this documentation, double-click the Model Composer IP, and click the Documentation button in the GUI.