HDL blocks that present an AXI4-Stream interface can be found in the Vitis Model Composer HDL Blockset Library entitled DSP/AXI4. Blocks in this library are drawn slightly differently from regular (non AXI4-Stream) blocks.
Port Groupings
Blocks that offer AXI4-Stream
interfaces have AXI4-Stream channels grouped
together and color coded. For example, on the DDS compiler 6.0 block shown above,
the input port data_tready, and the three output
ports, data_tvalid, data_tdata_sine, data_tdata_cosine
belong in the same AXI4-Stream channel.
Similarly, the input port config_tvalid, config_tdata_pinc and output port config_tready belong in the same AXI4-Stream channel. As does phase_tready, phase_tvalid, and
phase_tdata_phase_out.
Signals that are not part of any AXI4-Stream channels are given the same background color as the block;
aresetn is an example.
Port Name Shortening
In the example shown below, the AXI4-Stream signal names have been shortened to improve readability on the block. Name shortening is purely cosmetic and when netlisting occurs, the full AXI4-Stream name is used. Name shorting is turned on by default; you can uncheck the Display shortened port names option in the block parameter dialog box to reveal the full name.
Breaking Out Multi-Channel TDATA
In AXI4-Stream, TDATA can contain
multiple channels of data. In Model Composer, the individual channels for TDATA are
broken out. So for example, the TDATA of port dout
below contains both real and imaginary components.
The breaking out of multi-channel TDATA does not add additional logic to the design and is done in Model Composer as a convenience to the users. The data in each broken out TDATA port is also correctly byte-aligned.