Debugging Clock Propagation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

The top-level System Generator token can be used to control the display of all HDL Block Icons using the Block icon display control in the General tab. From this tab, you can either select Normalized sample periods or Sample frequencies to help understand how clocks get propagated in the design.

For multiple clock designs, the behavior of Normalized sample periods, is that the smallest Simulink system period is used to normalize all the sample periods in the design.

Figure 1. Debugging Clock Propagation

To enable the above display, set the Block icon display of the top-level System Generator token to Normalized Sample Periods and press Apply.

For Sample Frequencies, the port icon text display is the result of the following computation:

(1e6/FPGA clock period) * Simulink system period/Port sample period

where FPGA clock period is the FPGA clock period specified in ns in the domain’s System Generator token, and Simulink system period is the Simulink system period in seconds specified in the domain’s System Generator token.

The Sample Frequencies can also be used to validate correct clock propagation as shown in the following figure:

Figure 2. Sample Frequencies

To ensure that the simulation models the hardware behavior relatively with respect to the clocks, the ratio of Simulink system period to FPGA clock period in each domain must be the same. If this relationship is not complied with the correct ratio, a warning is thrown to indicate this problem as shown in the figure below:

Figure 3. Warning