Transceiver (SerDes) Modes - 2.4 English

The DCMAC Subsystem is capable of interfacing with the AMD Versal™ GTY/GTYP and GTM transceivers through the programmable logic region. Each GT Quad lane has a dedicated transceiver interface on the DCMAC Subsystem.

The DCMAC Subsystem has PCS/PMA lane logic functions including bit muxing, gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the DCMAC Subsystem must be configured to operate in RAW mode. The default transceiver lane interface configuration is 80b RAW interface for 26.5625 Gb/s lane logic.

For multi-lane PMD lane data rates of 200GE or 400GE with 100 Gb/s lane rate, the DCMAC Subsystem GT Quad interface can support per-lane GT Quad recovered clocks in the RX direction. This option reduces transceiver latency and improves 1588 timestamping accuracy at the cost of requiring per-lane FPGA clocking resources.

For designs in which it is preferred to reduce the clocking resources consumed by the DCMAC Subsystem link, the IP also supports having the transceivers configured with per-lane deskew buffering enabled, allowing all RX PMD lanes to share a common master lane clock.

The following table shows a list of DCMAC Subsystem-supported interface options for GT transceivers including the associated line rates, GT datapath width, and clock frequency.

The following table shows a list of DCMAC Subsystem-supported interface options for FEC-only mode, including the associated data rates, datapath width, and clock frequency.