Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369) - 2.4 English

Document ID: PG369
Release Date: 2024-08-05
Version: 2.4 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Features Summary
Protocol Support
Interfaces
Statistics
Additional Features
Applications
Licensing and Ordering
Product Specification
Standards
Performance and Resource Utilization
Operating Modes
MAC/PHY Independence
Port Data Rate
AXI4-Stream Modes
AXI4-Stream for Coupled MAC+PCS Mode
AXI4-Stream for Independent MAC and PCS+FEC Mode
Port FEC Modes
Transceiver (SerDes) Modes
Transceiver Clocking Modes
Flex Interface Modes
Flex Interface Modes of Operation
Flex Interface Receive Operating Modes
Flex Interface Transmit Operating Modes
MAC Interface Modes
MAC Interface Receive Operating Modes
MAC Interface Transmit Operating Modes
Port Descriptions
AXI4-Stream Interface
AXI4-Stream Interface Signaling
AXI4-Stream Interface Signaling for 100G Operation
AXI4-Stream Interface Signaling for 200G Operation
AXI4-Stream Interface Signaling for 400G Operation
AXI4-Stream Interface Signaling for Channelized 600G Operation
AXI4-Stream Interface Signaling for Channelized 400G Operation
Flex Interface
Flex Interface Signaling
Flex Interface Signaling for 100G PCS Operation
Flex Interface Signaling for 200G PCS Operation
Flex Interface Signaling for 400G PCS Operation
Flex Interface Signaling for 100G FlexO Operation
Flex Interface Signaling for 200G FlexO Operation
Flex Interface Signaling for 400G FlexO Operation
Flex Interface Signaling for 100G FEC-Only Operation
Flex Interface Signaling for 50G FEC-Only Operation
Flex Interface Signaling for 128GFC Operation
MAC Interface
Transceiver (SerDes) Interface
Transceiver Signaling
Transceiver Signaling for 100G Operation
Transceiver Signaling for 200G Operation
Transceiver Signaling for 400G Operation
Transceiver Signaling for 50G Operation
AXI4-Lite Register Interface
AXI4-Lite Clock and Reset
Control Ports
Status Ports
Statistics Ports
MAC Statistics TDM Ports
PCS Statistics TDM Ports
RS-FEC Statistics TDM Ports
Timestamp Interface
Timestamp Ports
Pause Frame Interface
Register Space
Memory Map
Configuration Registers
Status Registers
Statistics Monitoring
Per-Port Statistics Monitoring
Per-Channel Statistics Monitoring
Attributes
Power-Only Attributes
Designing with the Subsystem
General Design Guidelines
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking
Clocks
System Clocks
Transmit Clocks
Receive Clocks
Clocking Relationships
Resets
Reset Port Description
GT Reset Control Ports
User Interfaces
AXI4-Stream Interface
Transmit Operation
Transmit Segmented AXI4-Stream
Normal Transmission
Aborting a Transmission
Almost Full
Transmit Channelized Segmented AXI4-Stream
Operational Rules
Bus Operation Example
Aborting a Transmission
Receive Operation
Receive Segmented AXI4-Stream
Normal Receive
Frame Receive with Errors
Receive Channelized Segmented AXI4-Stream
Bus Operation Example
Frame Receive with Errors
Flex Interface
Flex Interface Examples
PCS Modes
FEC-Only and FlexO Modes
MAC Interface
Transmit MAC Interface
Channel Request
Data Output
Receive MAC Interface
Statistics Interfaces
AXI4-Lite Interface
MAC Statistics TDM Interface
PCS Statistics TDM Interface
RS-FEC Statistics TDM Interface
Pause Operation
TX Pause Generation
RX Pause Termination
Identifying Pause Packets
Receive Pause Quanta Presentation Interface
Enabling Receive Pause Timers
Receive Pause Timer Handshaking Interface
IEEE 1588 Timestamping Support
Overview
Timestamping
Egress Timestamping
1-Step Insertion
2-Step Insertion
Ingress Timestamping
Flex Interface Timestamping
Timer Operation
Timer Block Diagram
Time Representation
Timer Adjustment Mechanisms
Overwrite Interface
Adjustment Interface
Examples
Timer Monitoring
Operational Guidelines
Startup Procedures
Transmit Fixed Ethernet Startup Procedure when Using tx_core_reset
Transmit Fixed Ethernet Startup Procedure when Reconfiguring (not using tx_core_reset)
Receive Fixed Ethernet Startup Procedure when Using rx_core_reset
Receive Fixed Ethernet Startup Procedure when Reconfiguring (not using rx_core_reset)
Transmit Channel Flush in Independent MAC and PCS+FEC
Decommissioning a Port or Channel when not in Use
Custom Alignment Marker Setting
100GE for Ethernet mode
200GE for Ethernet Mode
400GE for Ethernet Mode
Design Flow Steps
GT Quad Integration with AMD IP Cores
Customizing and Generating the Subsystem
DCMAC Configuration Tab
GT Info and Parameters Tab
User Parameters
Output Generation
Constraining the Subsystem
Simulation
Synthesis and Implementation
Example Design
Example Design Hierarchy
DCMAC-GTM Clocking Architecture
DCMAC FEC Only Configuration Example Design
TX Traffic Generator
RX Traffic Checker
Error Injector
Skew Injector and Lane Re-order
REGMAP
AXI4 LITE Registers
Transceiver Selection Rules
User Interface
Simulating the Example Design
Supported Simulators
Running a Simulation
Simulation Speed Up
Synthesizing and Implementing the Example Design
PTP 1588 Timer Syncer IP
Upgrading
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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