Simulating the Example Design - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

The example design provides a quick way to simulate and observe the behavior of the DCMAC IP subsystem example design projects generated using the AMD Vivado™ Design Suite.