AXI4-Stream Interface Signaling for Channelized 400G Operation - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

Channelized segmented AXI4-Stream 400G operation uses a 1536-bit data bus with reduced clock frequency. The signaling is the same as in the table for Channelized 600G AXI4-Stream Interface Signaling.