The AXI4-Lite interface has its own clock and
reset. The AXI4-Lite clock
(
s_axi_aclk) is independent of the remainder of the DCMAC Subsystem clocks and can be any frequency to a maximum of 300
MHz.Important: The AXI4-Lite clock
must be present and stable for the DCMAC Subsystem to operate.
An interruption in the AXI4-Lite clock is
likely to result in an unrecoverable internal DCMAC Subsystem
error. When the AXI4-Lite clock has returned
and is stable, a full reset sequence is required to bring the DCMAC Subsystem back to a stable condition.
Asserting the AXI4-Lite
s_axi_areset
DCMAC Subsystem pin results in the following:- A reset of the AXI4-Lite port and DCMAC Subsystem APB3 control logic, stopping any in-flight writes/reads.
An AXI4-Lite reset does not reset the internal configuration registers.