Independent MAC and PCS+FEC mode uses a segmented AXI4-Stream interface that is channelized (time-sliced) in nature. Up to 600 Gb/s of total bandwidth is divisible in user-defined increments among 40 channels.
The entire 1536-bit AXI4-Stream interface is composed of 12 segments of 128 bits. Each clock cycle contains the data for a single channel. On the transmit path, there is a pre-indication from the DCMAC Subsystem of the channel ID for a given clock cycle. The user logic is responsible for driving data according to the same sequence of channel IDs. The rate of transmit path data flow is regulated through per-channel signaling from the DCMAC Subsystem that requests the user logic to skip a slot in the sequence. On the receive path, no backpressure is supported and the user logic must accept the data according to the channel IDs as output by the DCMAC Subsystem.