The straightforward available adjustment method is to perform a direct
update of the system_timer using the Overwrite interface.
In this procedure, the user logic provides its current timer value at regular intervals. The
per-port inputs D_ptp_systemtimer_N are used to provide the
master clock value. A transition on D_ptp_st_sync_N
triggers the overwrite. Both of these signals are latched on the master time-of-day clock,
ts_D_clk_N.
The overwrite mechanism is very effective. Using an overwrite interval of 64
ns and the default settings for the timer_increment allows
the DCMAC Subsystem to maintain the target accuracy even
with the clock at ±200 PPM.
D_ptp_systemtimer_N value using the ctl_D_st_offset_N input. This allows the system to account for any system
latency (for example, latency due to resampling delays). It also provides a way to move the
reference plane, the point in the datapath that the
timestamp represents. When the master time-of-day clock domain ts_D_clk_N and the D_ptp_st_sync_N signals are
asynchronous to the local clock, it is possible that the new system timer value is retimed
and sampled in the wrong clock cycle, leading to unwanted inaccuracy. To counter this, an
embedded DDR phase detector automatically adjusts the provided system_timer value to account for whether the new timer value was sampled on a
rising or falling clock edge. This is the phase adjust
function depicted in the timer block diagram.
If additional accuracy is required, the user logic can overwrite the system
timer at start-up and then continually monitor the D_ptp_systemtimer_N_out making frequency and phase adjustments to the system
timer as necessary to precisely match the master timer. Using this method, accuracy can be
improved significantly.