AXI4-Stream Interface Signaling for Channelized 600G Operation - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

Channelized segmented AXI4-Stream 600G operation uses a 1536-bit data bus.

Note: In this table, <M> is the segment number 0 to 11.
Table 1. Channelized 600G AXI4-Stream Interface Signaling
Port Segments(s) Interface Function Signaling
0 M=0…11 RX AXI-S valid rx_axis_tvalid_0
channel_id[5:0] rx_axis_tid[5:0]
preamble_out_0[55:0] rx_preambleout_0[55:0]
preamble_out_1[55:0] rx_preambleout_1[55:0]
preamble_out_2[55:0] rx_preambleout_2[55:0]
seg<M>_data[127:0] rx_axis_tdata<M>[127:0]
seg<M>_ena rx_axis_tuser_ena<M>
seg<M>_sop rx_axis_tuser_sop<M>
seg<M>_eop rx_axis_tuser_eop<M>
seg<M>_err rx_axis_tuser_err<M>
seg<M>_mty[3:0] rx_axis_tuser_mty<M>[3:0]
0 M=0…11 TX AXI-S channel_status_valid tx_axis_ch_status_vld
channel_status_id[5:0] tx_axis_ch_status_id[5:0]
channel_status_skip_request tx_axis_ch_status_skip_req
channel_status_skip_response tx_axis_tuser_skip_response
request_id_vld tx_axis_id_req_vld
request_id[5:0] tx_axis_id_req[5:0]
valid tx_axis_tvalid_0
channel_id[5:0] tx_axis_tid[5:0]
preamble_in_0[55:0] tx_preamblein_0[55:0]
preamble_in_1[55:0] tx_preamblein_1[55:0]
preamble_in_2[55:0] tx_preamblein_2[55:0]
seg<M>_data[127:0] tx_axis_tdata<M>[127:0]
seg<M>_ena tx_axis_tuser_ena<M>
seg<M>_sop tx_axis_tuser_sop<M>
seg<M>_eop tx_axis_tuser_eop<M>
seg<M>_err tx_axis_tuser_err<M>
seg<M>_mty[3:0] tx_axis_tuser_mty<M>[3:0]