Normal Transmission - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

In the following figure, a typical sequence of frame transmits is shown. This is a 400G/8-segment bus as an example. Segments 2 through 6 are not shown to keep the diagram compact.

Figure 1. AXI4-Stream Typical Sequence of Frame Transmits
The highlights of this sequence of operations are as follows:
  1. In cycle #3, a new frame (frame A) is started in segment 0. Frame A is 158 bytes long (nine full segments, plus a final segment containing 14 bytes (two empty)). The user logic driving in frame A asserts ena0 and sop0 along with the first 16 bytes of data, A0. Preamble is provided on the tx_preamblein_0 port. The frame continues in segments 1–7.
  2. In cycle #4, frame A continues in segment 0 but ends in segment 1 when eop is asserted. The mty signal indicates the number of unused bytes in this segment (4’h2 in this case). A new frame, frame B (FRM-B), begins in segment 2 (idle segment gaps are not permitted) and ends in segment 6 (five segments total, so the frame is between 65 and 80 bytes; details not shown). Because the sop for FRM-B is within segments 0-3, the tx_preamblein_0 provides the preamble.
  3. Frame C begins in segment 7 of cycle #4; its preamble is provided on tx_preamblein_2 because the sop is within segments 4–7.
  4. Frame C continues through cycle #5 across all segments (data C1 through C8).
  5. In cycle #6, frame C ends in segment 7 with data C16. The eop signal is asserted in this segment and the mty field indicates five unused bytes.
  6. In cycle #7, a new frame, frame D, is initiated. However, the AXI4-Stream interface has deasserted tx_axis_tready_0. The user logic must hold the inputs until tx_axis_tready_0 is asserted again.
  7. In cycle #8 the tready signal has been asserted again and so the transfer is accepted. Frame D begins in segment 0 (sop asserted) and continues through to segment 7.
  8. Frame D continues in cycle #9, across segments 0 through 7.
  9. In cycle #10, frame D ends in segment 0 with the assertion of eop. The user logic does not have any more data to send so it keeps ena deasserted in segments 1 through 7.
  10. In the subsequent cycle, #11, there is no data at all to send, so the user logic deasserts tx_axis_tvalid_0 to indicate that the bus is completely idle.
  11. In cycle #12 segment 0, a new frame – frame E – begins. The user logic asserts tx_axis_tvalid_0 again. Frame E continues through to segment 7.
  12. Frame E continues in cycle #13 and beyond.