AXI4-Stream Interface - 2.4 English

In each direction (transmit and receive), there are two possible AXI modes set by the GLOBAL_MODE register:

• Coupled MAC+PCS mode: segmented AXI4-Stream
• Independent MAC and PCS+FEC mode: channelized segmented AXI4-Stream

The total number of 16-byte AXI4-Stream segments available on the DCMAC Subsystem is 12. Channelized segmented AXI4-Stream always uses all 12 segments and the aggregate throughput is determined by clock frequency. In some parts, the maximum clock frequency is reduced and the channelized segmented AXI4-Stream bandwidth is capped at 400G; however, this is not mode selected but a function of clock rate.

When Coupled MAC+PCS mode is selected, the number of segments assigned to a given port is determined first by the chosen AXI-S width and secondarily by the data_rate controls. There are two AXI-S width options, normal width or double (2x) width, which are selectable in the GLOBAL_MODE register (ctl_tx_axis_cfg, ctl_rx_axis_cfg). When in wide AXI-S mode (which allows use of a reduced clock frequency), the data_rate controls are ignored and the AXI4-Stream bus is configured for three ports (100G per port), each with four segments (allowing up to one frame per cycle to be transferred).

When in normal AXI-S width mode, the data rate controls (in the C0_TX_MODE_REG, C2_TX_MODE_REG, C4_TX_MODE_REG, C0_RX_MODE_REG, C2_RX_MODE_REG, C4_RX_MODE_REG registers) determine the number of segments assigned to a port:

• c0_ctl_rx_data_rate[1:0] and c0_ctl_tx_data_rate[1:0]
  • 2’d2 / 400G: Port 0 with eight segments
    • Up to two frames per cycle
    • Ports 1, 2, and 3 disabled
  • 2’d1 / 200G: Port 0 with four segments
    • Maximum of one frame per cycle
    • Port 1 disabled
  • 2’d0 / 100G: Port 0 with two segments
    • Maximum of one frame every two cycles
    • Port 1 available – also with two segments
• c2_ctl_rx_data_rate and c2_ctl_tx_data_rate (only selectable if Port 0 is not in 400G mode)
  • 1’d1 / 200G: Port 2 with four segments
    • Maximum of one frame per cycle
    • Port 3 disabled
  • 1’d0 / 100G: Port 2 with two segments
    • Maximum of one frame every two cycles
    • Port 3 available – also with 2 segments
• c4_ctl_rx_data_rate and c4_ctl_tx_data_rate
  • 1’d1 / 200G: Port 4 with four segments
    • Maximum of one frame per cycle
    • Port 5 disabled
  • 1’d0 / 100G: Port 4 with two segments
    • Maximum of one frame every two cycles
    • Port 5 available – also with two segments

The following tables show the segments as 128-bit portions of the aggregate AXI4-Stream data bus and illustrate the configurations possible.