AXI4 LITE Registers - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The register map enables the user to control and collect statistics from DCMAC, the traffic generator and checker, and the error injector. It also provides access to the following statistics from DCMAC FEC. All addresses mentioned are relative to the base address or the C_S_AXI_BASE_ADDR parameter of the register map module.

Table 1. DCMAC Statistic Registers
Name Description
C<N>_STAT_RX_FEC_CW_LSB

(0x0E48+ (N+1)*0x1000)

Count of processed codewords on FEC port <N>.
C<N>_STAT_RX_FEC_CORRECTED_CW_LSB

(0x0E50 + (N+1)*0x1000)

Count of corrected codewords on FEC port <N>.
C<N>_STAT_RX_FEC_UNCORRECTED_CW_LSB

(0x0E58 + (N+1)*0x1000)

Count of uncorrected codewords on FEC port <N>.
C<N>_STAT_RX_FEC_CW_BH_LSB

(0x0E60 + (N+1)*0x1000)

Count of processed codewords on second 50G (bottom two PMA lanes) FEC port <N>.
C<N>_STAT_RX_FEC_CORRECTED_CW_BH_LSB

(0x0E68 + (N+1)*0x1000)

Count of corrected codewords on second 50G (bottom two PMA lanes) FEC port <N>.
C<N>_STAT_RX_FEC_UNCORRECTED_CW_BH_LSB

(0x0E70 + (N+1)*0x1000)

Count of uncorrected codewords on second 50G (bottom two PMA lanes) FEC port <N>.
  1. N represents the port number. There are six ports for 6x100G mode.