The DCMAC Subsystem contains a soft logic 32-bit AXI4-Lite interface block to allow access to the APB3 interface of the integrated IP. Through the AXI4-Lite interface, you can access the internal configuration, status, and statistics registers. For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).
| Port Name | I/O | Description |
|---|---|---|
| s_axi_aclk | I | This clock is used for both the AXI4-Lite
bridge soft logic and DCMAC Subsystem APB3 port
clock. Note: The s_axi_clk must be present for the
DCMAC Subsystem to function. If this clock
is interrupted, the DCMAC Subsystem enters an
error state.
|
| s_axi_areset | I | Active-High reset for the AXI4-Lite port. Asserting this reset alters the port control logic and stops any in-flight writes/reads. It does not reset the internal configuration registers with exceptions listed below. |
| s_axi_* | I/O | See the AXI to APB Bridge LogiCORE IP Product Guide (PG073) and the Vivado Design Suite: AXI Reference Guide (UG1037). |
| s_axi_pslverr | O |
DCMAC Subsystem
AXI4-Lite slave error indication.
This signal is Low during successful operation. When High, the
signal indicates an AXI bus protocol error has occurred. Note: Writes or reads to
non-existent/invalid register locations, nor a port being held
in reset, does not trigger a slave error
indication.
|
| tx_port_pm_tick[5:0] | I | Performance monitoring TX statistics tick signal for individual ports. |
| rx_port_pm_tick[5:0] | I | Performance monitoring RX statistics tick signal for individual ports. |
| tx_port_pm_rdy[5:0] | O | Performance monitoring TX statistics counters ready flag. These per-port flags indicate that the internal statistics engine has completed a user-directed update cycle and is ready for access. |
| rx_port_pm_rdy[5:0] | O | Performance monitoring RX statistics counters ready flag. These per-port flags indicate that the internal statistics engine has completed a user-directed update cycle and is ready for access. |
| tx_all_channel_mac_pm_tick | I | Performance monitoring TX statistics tick signal for all channels. |
| rx_all_channel_mac_pm_tick | I | Performance monitoring RX statistics tick signal for all channels. |
| tx_all_channel_mac_pm_rdy | O | Performance monitoring TX statistics counters ready flag. This all-channels flag indicates that the internal statistics engine has completed a user-directed update cycle and is ready for access. |
| rx_all_channel_mac_pm_rdy | O | Performance monitoring RX statistics counters ready flag. This all-channels flag indicates that the internal statistics engine has completed a user-directed update cycle and is ready for access. |
A complete description of the register map and the individual registers can be found in the Register Space section.