The DCMAC Subsystem receive channelized
segmented AXI4-Stream bus has a data movement portion directly
analogous to its transmit counterpart. The tdata,
tvalid, tid, and segment control fields
(ena, sop, eop,
err, mty) all have the same meaning and function.
The additional elements for channel sequencing (id_req and
id_req_valid) and backpressure control
(ch_status_vld, ch_status_id, and
ch_status_skip_req), however, are absent.
Channelized receive is different from transmit in that data is presented as it is
received on the active segments of receipt. There is no internal buffering or
realignment of received data; between eop signals and
sop signals (or on startup), any number of segments can be idle
(ena deasserted). Correspondingly, sop signals can
occur with any bus alignment, regardless of the location of a preceding
eop. The only guarantee is that when a frame starts
(ena and sop asserted), all segments for valid
AXI4-Stream cycles are enabled until eop. This
means that between sop and eop being asserted, all
segments for cycles in which tvalid is asserted have
ena asserted.
The allowance of idle segment (ena deasserted) gaps between frames on
the same cycle, or at the start of a new frame cycle, is also a significant difference
between the way the channelized segmented bus operates when compared to the
non-channelized segmented bus.