Transceiver Signaling for 100G Operation - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2024-08-05
Version
2.4 English
Note: In this table, fec_rx_din_start_*_bh signals are used only during 100G KR4 mode of operation.
Note: In this table, fec_tx_dout_start_*_bh signals are used only during 100G KR4 and 128GFC modes of operation.
Table 1. 6 x 100G Transceiver Signaling
Port Interface Active GT Clocks Active GT Interface Data Bus
0 RX SerDes IF
  • rx_serdes_clk[0]
  • rx_alt_serdes_clk[0]
 rx_serdes_data0[79:0]
rx_serdes_data1[79:0]
rx_serdes_data2[79:0]
rx_serdes_data3[79:0]
fec_rx_din_start_0
fec_rx_din_start_0_bh
rx_serdes_fifo_flagin_0
rx_serdes_fifo_flagout_0
rx_serdes_albuf_restart_0
rx_serdes_albuf_slip_0
rx_serdes_albuf_slip_1
rx_serdes_albuf_slip_2
rx_serdes_albuf_slip_3
TX SerDes IF
  • tx_serdes_clk[0]
  • tx_alt_serdes_clk[0]
 tx_serdes_data0[79:0]
tx_serdes_data1[79:0]
tx_serdes_data2[79:0]
tx_serdes_data3[79:0]
fec_tx_dout_start_0
fec_tx_dout_start_0_bh
tx_serdes_is_am_prefifo_0
tx_serdes_is_am_0
1 RX SerDes IF
  • rx_serdes_clk[1]
  • rx_alt_serdes_clk[1]
rx_serdes_data4[79:0]
rx_serdes_data5[79:0]
rx_serdes_data6[79:0]
rx_serdes_data7[79:0]
fec_rx_din_start_1
fec_rx_din_start_1_bh
rx_serdes_fifo_flagin_1
rx_serdes_fifo_flagout_1
rx_serdes_albuf_restart_1
rx_serdes_albuf_slip_4
rx_serdes_albuf_slip_5
rx_serdes_albuf_slip_6
rx_serdes_albuf_slip_7
TX SerDes IF
  • tx_serdes_clk[1]
  • tx_alt_serdes_clk[1]
 tx_serdes_data4[79:0]
tx_serdes_data5[79:0]
tx_serdes_data6[79:0]
tx_serdes_data7[79:0]
fec_tx_dout_start_1
fec_tx_dout_start_1_bh
tx_serdes_is_am_prefifo_1
tx_serdes_is_am_1
2 RX SerDes IF
  • rx_serdes_clk[2]
  • rx_alt_serdes_clk[2]
 rx_serdes_data8[79:0]
rx_serdes_data9[79:0]
rx_serdes_data10[79:0]
rx_serdes_data11[79:0]
fec_rx_din_start_2
fec_rx_din_start_2_bh
rx_serdes_fifo_flagin_2
rx_serdes_fifo_flagout_2
rx_serdes_albuf_restart_2
rx_serdes_albuf_slip_8
rx_serdes_albuf_slip_9
rx_serdes_albuf_slip_10
rx_serdes_albuf_slip_11
TX SerDes IF
  • tx_serdes_clk[2]
  • tx_alt_serdes_clk[2]
 tx_serdes_data8[79:0]
tx_serdes_data9[79:0]
tx_serdes_data10[79:0]
tx_serdes_data11[79:0]
fec_tx_dout_start_2
fec_tx_dout_start_2_bh
tx_serdes_is_am_prefifo_2
tx_serdes_is_am_2
3 RX SerDes IF
  • rx_serdes_clk[3]
  • rx_alt_serdes_clk[3]
rx_serdes_data12[79:0]
rx_serdes_data13[79:0]
rx_serdes_data14[79:0]
rx_serdes_data15[79:0]
fec_rx_din_start_3
fec_rx_din_start_3_bh
rx_serdes_fifo_flagin_3
rx_serdes_fifo_flagout_3
rx_serdes_albuf_restart_3
rx_serdes_albuf_slip_12
rx_serdes_albuf_slip_13
rx_serdes_albuf_slip_14
rx_serdes_albuf_slip_15
TX SerDes IF
  • tx_serdes_clk[3]
  • tx_alt_serdes_clk[3]
 tx_serdes_data12[79:0]
tx_serdes_data13[79:0]
tx_serdes_data14[79:0]
tx_serdes_data15[79:0]
fec_tx_dout_start_3
fec_tx_dout_start_3_bh
tx_serdes_is_am_prefifo_3
tx_serdes_is_am_3
4 RX SerDes IF
  • rx_serdes_clk[4]
  • rx_alt_serdes_clk[4]
 rx_serdes_data16[79:0]
rx_serdes_data17[79:0]
rx_serdes_data18[79:0]
rx_serdes_data19[79:0]
fec_rx_din_start_4
fec_rx_din_start_4_bh
rx_serdes_fifo_flagin_4
rx_serdes_fifo_flagout_4
rx_serdes_albuf_restart_4
rx_serdes_albuf_slip_16
rx_serdes_albuf_slip_17
rx_serdes_albuf_slip_18
rx_serdes_albuf_slip_19
TX SerDes IF
  • tx_serdes_clk[4]
  • tx_alt_serdes_clk[4]
 tx_serdes_data16[79:0]
tx_serdes_data17[79:0]
tx_serdes_data18[79:0]
tx_serdes_data19[79:0]
fec_tx_dout_start_4
fec_tx_dout_start_4_bh
tx_serdes_is_am_prefifo_4
tx_serdes_is_am_4
5 RX SerDes IF
  • rx_serdes_clk[5]
  • rx_alt_serdes_clk[5]
rx_serdes_data20[79:0]
rx_serdes_data21[79:0]
rx_serdes_data22[79:0]
rx_serdes_data23[79:0]
fec_rx_din_start_5
fec_rx_din_start_5_bh
rx_serdes_fifo_flagin_5
rx_serdes_fifo_flagout_5
rx_serdes_albuf_restart_5
rx_serdes_albuf_slip_20
rx_serdes_albuf_slip_21
rx_serdes_albuf_slip_22
rx_serdes_albuf_slip_23
TX SerDes IF
  • tx_serdes_clk[5]
  • tx_alt_serdes_clk[5]
 tx_serdes_data20[79:0]
tx_serdes_data21[79:0]
tx_serdes_data22[79:0]
tx_serdes_data23[79:0]
fec_tx_dout_start_5
fec_tx_dout_start_5_bh
tx_serdes_is_am_prefifo_5
tx_serdes_is_am_5