The DCMAC FixedE path employs an internal time-sliced MAC that is a channelized core. When adding, removing, or reconfiguring ports, it is usually not appropriate to do a global reset (rx_core_reset). Instead, individual ports can be reset/cleared/flushed independently. Port flushes (and corresponding PHY resets) on reconfigured ports should not affect other active ports that are not being reconfigured.
- Assert rx_channel_flush and rx_serdes_reset on any active ports that are being reconfigured (or deactivated)
- Assert rx_channel_flush and rx_serdes_reset on any inactive ports that are being reconfigured to become active
- Wait for 50 (minimum) core clock cycles
- or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual)
- Release rx_channel_flush for active ports
- Wait for 50 (minimum) core clock cycles
- or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual)
- Release rx_serdes_reset for active ports