preambleout buses available.
The rx_preambleout_0 bus is used for frames starting in
segments 0 to 3, while rx_preamblein_2 is used for
frames starting in segments 4 to 7. rx_preamblein buses are only used in non-channelized 100G
modes.As is the case with transmit, new sop signals on receive are guaranteed
to be aligned to segment 0. New is defined as either the first
frame after port startup, or the start of a frame when the last valid cycle ended with
an eop (on any segment, but correspondingly followed by disabled
segments if eop was not on the last segment of the bus).
Start-of-packet indications can occur on other segments, but only if they immediately
follow an eop on the preceding segment. There can be no gaps (that is,
segments with ena deasserted) between eop and
sop on a single cycle.
A key difference between transmit and receive is that there is no tready
available for client backpressure on the RX AXI4-Stream interface.
The DCMAC Subsystem has no buffering capacity to absorb
client backpressure and the result is that data is always relayed when
tvalid is asserted. If backpressure is needed, the necessary
buffering must be implemented in user logic.
Another difference is that tvalid might not
remain asserted for the duration of a frame transfer. Between sop and eop, all segments of
valid cycles are enabled, but not all cycles will necessarily be valid.
This is due to the asynchronous relationship between the line clocks, the receive core
clock, and the AXI clock. Without internal buffering to ensure frame continuity, the
asynchronous clock relationships sometimes result in a lack of data to present on the
AXI interface, and the result is a temporary pause between the cycles of an ongoing
frame.