AXI4-Stream for Coupled MAC+PCS Mode - 2.5 English - PG369

Coupled MAC+PCS mode is often called standard Fixed Ethernet (FixedE) mode. When configured in this mode, the AXI4-Stream interface operates in non-channelized segmented mode that ensures high throughput over a range of traffic profiles. The interface is dynamically reconfigurable during runtime to support multiple modes of Ethernet operation. The DCMAC Subsystem AXI4-Stream interface supports up to a total of 600 Gb/s bandwidth. It can be configured as six independent 100 Gb/s AXI4-Stream interfaces. Alternatively, the portions of the AXI4-Stream interface can be ganged together to deliver individual AXI4-Stream interface rates of 200 Gb/s or 400 Gb/s, in addition to combinations of 100 Gb/s, 200 Gb/s and 400 Gb/s.

The AXI4-Stream interface data rates are configured using the following fields:

• The c0_ctl_tx_data_rate, c2_ctl_tx_data_rate, and c4_ctl_tx_data_rate fields of the C0_TX_MODE_REG, C2_TX_MODE_REG, and C4_TX_MODE_REG for TX.
• The c0_ctl_rx_data_rate, c2_ctl_rx_data_rate, and c4_ctl_rx_data_rate fields of the C0_RX_MODE_REG, C2_RX_MODE_REG, and C4_RX_MODE_REG registers for RX.

These can be configured dynamically, provided traffic is not flowing on the corresponding portions of the AXI4-Stream interface.

ctl_tx_pcs_active_ports: {bit_offset: 16, bit_width: 3, reset: 3'h5}.

For FixedE mode, identifies the number of active receive ports minus one (where the port refers to the internal resources that provide 100G of bandwidth). The following three values are valid:

• 3'h5 for 600G total Ethernet bandwidth in all combinations (for example 6x100GE, 2x100GE + 2x200GE)

• 3'h3 for 1x400GE

• 3'h2 for 3x100GE in wide AXI mode (see ctl_tx_axis_cfg).

Changing the value of this field is only required for wide AXI mode (in which case, the value must be 3’h2); for normal operation, a value of 3’h5 offers the full range of DCMAC’s capability and is the confirmed correct setting for all modes/rates and combinations of active and inactive ports. If there is an application need to change this setting (under guidance from AMD) to 3'h3 (exclusive 1x400GE), the core clock must be correspondingly derated. ctl_rx_pcs_active_ports will also change correspondingly.

The AXI clock frequencies in the following table are required to meet bandwidth for a given Ethernet interface.