References - 2.5 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2025-02-12
Version
2.5 English
These documents provide supplemental material useful with this guide:
  1. IEEE Standard for Ethernet (IEEE Std 802.3-2022)
  2. IEEE Standard 1588-2008, IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems
  3. 802.3cd-2018 - IEEE Standard for Ethernet - Amendment 3: Media Access Control Parameters for 50 Gb/s and Physical Layers and Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operation
  4. IEEE 802.3ck-2022:IEEE Standard for Ethernet Amendment 4: Physical Layer Specifications and Management Parameters for 100 Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Based on 100 Gb/s Signaling
  5. ITU-T G.709.1/Y.1331.1 (06/2018) – Flexible OTN short-reach interfaces
  6. IA Flex Ethernet 2.1 Implementation Agreement (OIF FLEXE-02.1)
  7. Arm® AMBA® 4 AXI4-Stream Protocol v1.0 Specification (ARM IHI 0051A)
  8. Arm AMBA 3 APB v1.0 Specification (ARM IHI 0024B)
  9. AXI to APB Bridge LogiCORE IP Product Guide (PG073)
  10. Vivado Design Suite: AXI Reference Guide (UG1037)
  11. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
  12. Vivado Design Suite User Guide: Designing with IP (UG896)
  13. Vivado Design Suite User Guide: Getting Started (UG910)
  14. Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)
  15. Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314)
  16. Vivado Design Suite User Guide: Programming and Debugging (UG908)
  17. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
  18. Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
  19. Vivado Design Suite User Guide: Logic Simulation (UG900)