Clocks - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

The following table lists the clocks that are present in the DCMAC Subsystem.

Table 1. Clocks
Clock Port Description Nominal Frequency Range (MHz) 1 Overclocked Rate (MHz) Superscript 2
AXI4-Lite s_axi_clk AXI4-Lite processor interface clock. 50 - 300 300
AXI

tx_axi_clk

rx_axi_clk

AXI4-Stream interface clocks. These clocks are used by the AXI4-Stream interface. They are also used by a number of device statistics and flow control signals. 195.3125 - 390.625 415.2512
core

tx_core_clk

rx_core_clk

High-speed clocks which drive internal core logic. 390.625 -782 830.502
serdes tx_serdes_clk[5:0]

rx_serdes_clk[5:0]

Per-port high-speed clocks for the GT interface. 644.5313 - 664.0625 705.25 3
700 4
alt_serdes tx_alt_serdes_clk[5:0]

rx_alt_serdes_clk[5:0]

Per-port alternate low-frequency clocks for the GT interface. 322.2656 - 332.0313 352.625 3
350 4
gt_usrclk gt_tx_usrclk[5:0] gt_rx_usrclk[5:0] Per-port GT Interface clock. Applicable only for 256-bit (Full Density) configs. 415.039 437.5
flexif tx_flexif_clk[5:0]

rx_flexif_clk[5:0]

Per-port FLEX I/F clocks. 312.50 - 390.625 427.4242
macif tx_macif_clk

rx_macif_clk

MAC I/F clocks. 260.4167 - 390.625 415.2512
ts

ts_clk[5:0]

Per-port clocks for the timestamp interface. 50 - 350 350.000
  1. Across all operational modes of the DCMAC Subsystem. Required frequency depends on operational mode.
  2. The Overclocked Rate options are supported with -2 and higher speed grade devices.
  3. For transceiver lane serial rate up to 56.42 Gb/s.
  4. For transceiver lane serial rate beyond 56.52 Gb/s and up to 112 Gb/s.