PCS Modes - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

In this example, data transfer into the FLEX I/F port is active on Client 0 and 2. Client 0 is 100GE in raw mode (c0_ctl_flexif_select==0). The user logic drives data (tx_flex_data_0) into the interface while asserting tx_flex_ena_0. In this mode, the user provides the alignment markers, which are indicated by tx_flex_am_flag_0. Client 2 is 200GE in one of the other PCS modes. In this case, the user logic can indicate where the AM should go by asserting tx_flex_am_flag_2. The AM is inserted just before the data on this cycle. The ability to specify the AM location is enabled by asserting c2_ctl_tx_flexif_am_mode.

Notice the relationship between the per-port tx_flex_stall_<N> signal and tx_flex_ena_<N>. The stall signal is output to backpressure the transfers into the FLEX I/F. For the stall signal, you must stall (drop the enable) for the same number of cycles that the stall signal is asserted (within two cycles). For example, if the stall signal is High for one cycle, drop the enable signal for one cycle. The enable should follow the stall by a fixed number (0-2) of cycles (except inverted).

Figure 1. TX PCS Flex Interface

In the receive direction, the FLEX I/F outputs data at the configured port rate. Valid data is indicated by the per-client signal rx_flex_ena_<N>. When rx_flex_ena_<N> is deasserted, the data is invalid. There is no backpressure from the user logic back to the FLEX I/F port. The user logic must be able to keep up with the selected data rate. In the following example, client 0 is 400GE. The AM position is indicated by rx_flex_amflag_0. Client 4 is 128GFC (c4_ctl_rx_flexif_select==0 and and c4_ctl_rx_fec_mode == 5'b01000). In this mode, the AM is provided and indicated with rx_flex_amflag_4.

Note: For the FLEX I/F, rx_flex_ena0 controls 200G Client 0, rx_flex_ena2 controls 200G Client 2, and rx_flex_ena4 controls 200G Client 4. While rx_flex_ena0 controls 400G Client 0.
Figure 2. RX PCS Flex Interface
The rx_flex_startb_<N> signal is used to indicate the RX status. The user logic can use the status signal to switch to a locally timed and generated local fault if desired.
Important: Check that the status signal is stable for at least two enabled cycles before taking action.

In PCS only mode, on the Flex Interface data on port[0] begins on rx_flex_data0[0]. The beginning of the waveform shows idles on the data. The first 66-bit block is on bits 65:0 and idle is “2 78 00 00 00 00 00 00 00”.

With the DCMAC FLEXIF configured to have port 0 enabled as 100G 4x66, the data is on rx_flex_data_0[263:0].

  • The first block is bits 65:0, with data in bits 63:0 and header in bits 65:64.
  • The second block is bits 131:66, with data in bits 129:66 and header in bits 131:130.
  • The third block is bits 197:132, with data in bits 195:132 and header in bits 197:196.
  • The fourth block is bits 263:298, with data in bits 261:198 and header in bits 263:262.

In the waveform, the data is broken into 64/66 bit blocks to be easier to view. The following figure shows an incoming packets with data in 65:0 bit order and 0:63 bit order. This waveform is from a MAC configured for 100G and ctl_rx_flexif_select bits 1:0 = 11 for PCS mode.