The PTP timer runs on an internal SerDes clock which might be too fast to use in
the programmable logic (PL). The ptp_st_sync_out signal
indicates when the ptp_systemtimer_out value is valid.
The source of these signals are aligned internally (see the following diagram). The
internal version of ptp_st_sync_out is registered once
with an output flop clocked on the SerDes clock. The internal source of ptp_systemtimer_out is captured using the retimed (to SerDes
clock) version of the ptp_st_sync input. Next, the timer
value is synchronized from the SerDes clock to the ts_clk.
For most applications, you can simply retime ptp_st_sync_out to the PL clock, and use it to capture ptp_systemtimer_out. If you need to determine the phase
relationship between the internal system timer and a PL time of day with a very high
degree of accuracy (say within 1 ns or less), you can measure the phase offset by using
a phase detector (of their your own design) on an asynchronous clock (or SerDes clock)
on the ptp_st_sync_out output (accounting for the
additional SerDes clock cycle of the internal output flop). Sampling over multiple edges
can be done and averaged to get an even higher level of accuracy.
