Skew Injector and Lane Re-order - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

The skew injector and lane re-order block add an amount of delay in each SerDes lane so that the data from each SerDes lane is aligned. The logic inside this block is also responsible for re-ordering the TX SerDes lanes so that the RX SerDes lanes can detect the corresponding wire for each SerDes lane.