Flex Interface Signaling for 400G PCS Operation - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-11-08
Version
2.3 English
FLEX I/F 400G PCS operation uses a 16 x 66-bit data bus. Only one 400G port can be active.
Table 1. 1 x 400G PCS Signaling for Flex Interface
Port Interface Function Signaling
0 RX FLEX I/F enable rx_flex_ena_0
amflag indicator rx_flex_amflag_0
lane0 indicator rx_flex_lane0_0
ptp_tstamp[31:0] for data[527:0] rx_ptp_tstamp_out_0[31:0]
ptp_tstamp[31:0] for data[1055:528] rx_ptp_tstamp_out_2[31:0]
data[263:0] rx_flex_data_0[263:0]
data[527:264] rx_flex_data_1[263:0]
data[791:528] rx_flex_data_2[263:0]
data[1055:792] rx_flex_data_3[263:0]
TX FLEX I/F enable[263:0] tx_flex_ena_0
amflag indicator tx_flex_amflag_0
ptp_tag_field[7:0] for data[527:0] tx_ptp_flex_tag_field_in_0[7:0]
ptp_1588loc[2:0] for data[527:0] tx_ptp_flex_1588loc_in_0[2:0]
ptp_1588op for data[527:0] tx_ptp_flex_1588op_0
ptp_tag_field[7:0] for data[1055:528] tx_ptp_flex_tag_field_in_0[7:0]
ptp_1588loc[2:0] for data[1055:528] tx_ptp_flex_1588loc_in_0[2:0]
ptp_1588op for data[1055:528] tx_ptp_flex_1588op_0
stall[263:0] tx_flex_stall_0
data[263:0] tx_flex_data_0[263:0]
data[527:264] tx_flex_data_1[263:0]
data[791:528] tx_flex_data_2[263:0]
data[1055:792] tx_flex_data_3[263:0]