Recognize Timing Critical Signals

Recognize Timing Critical Signals - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID

PG369

Release Date

2024-08-05

Version

2.4 English

The constraints provided with the example design identify the critical signals and timing constraints that should be applied.