Port FEC Modes - 2.4 English

Forward error correction (FEC) is available on the PHYs of the DCMAC Subsystem port. FEC can be enabled or disabled on a per-port basis.

For the transmit path, the various FEC operating modes are selected through the following fields of the C0_TX_MODE_REG through C5_TX_MODE_REG registers:

• c0_ctl_tx_fec_mode
• c1_ctl_tx_fec_mode
• c2_ctl_tx_fec_mode
• c3_ctl_tx_fec_mode
• c4_ctl_tx_fec_mode
• c5_ctl_tx_fec_mode

Likewise, on the receive path, the FEC modes are selected using the following fields of the C0_RX_MODE_REG through C5_RX_MODE_REG registers:

• c0_ctl_rx_fec_mode
• c1_ctl_rx_fec_mode
• c2_ctl_rx_fec_mode
• c3_ctl_rx_fec_mode
• c4_ctl_rx_fec_mode
• c5_ctl_rx_fec_mode

Furthermore, the 256B/257B transcoder can be bypassed in the transmit path using the c0_ctl_tx_fec_transcode_bypass through c5_ctl_tx_fec_transcode_bypass fields of the corresponding C0_TX_MODE_REG through C5_TX_MODE_REG registers. The same can be done in the receive path using the c0_ctl_rx_fec_transcode_bypass through c5_ctl_rx_fec_transcode_bypass fields of the corresponding C0_RX_MODE_REG through C5_RX_MODE_REG registers.

In the receive path only, the lane alignment logic can be bypassed using the c0_ctl_rx_fec_alignment_bypass through c5_ctl_rx_fec_alignment_bypass fields of the corresponding C0_RX_MODE_REG through C5_RX_MODE_REG registers.

A change in either of these registers requires a reset being driven to that port after configuration is complete.

Deskew buffers are shared across FEC modes. For FEC modes such as 128GFC and FlexO, whose data rate exceeds Ethernet nominal rate, the DCMAC Subsystem can handle an equivalent number of bits of skew. Because the bit rate of 128GFC and FlexO is higher, this translates into less than 180 ns of deskew capability.  Specially, 128GFC supports 175 ns of deskew and FlexO supports 176 ns of deskew.  Applications requiring additional deskew capability can make use of an external alignment buffer to deskew the data prior to its entry into the DCMAC Subsystem.  The DCMAC Subsystem provides rx_serdes_albuf_slip_<4*N+0> through rx_serdes_albuf_slip_<4*N+3> signals to simplify user logic related to this external alignment buffer.

Many FEC modes are relevant for both Coupled MAC+PCS and Independent MAC and PCS+FEC modes. The following table summarizes the available configurations for each DCMAC Subsystem port.