Status Ports - 2.5 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2025-02-12
Version
2.5 English

In addition to the AXI4-Lite registers and counters, the DCMAC Subsystem provides status flag ports to enable ease of integration into user monitoring and interrupt logic. The following table has a list of the output status flags. All status ports are outputs.

Table 1. DCMAC Subsystem Status Port Descriptions
Port Name Clock Domain I/O Description
rx_fec_am_sf_0[2:0] rx_alt_serdes_clk[0] O For 200GE/400GE, these are the rx_am_sf degrade bits from the AM.

This signal is updated within 10 clock cycles after rx_flex_amflag_0 is pulsed.

rx_fec_am_sf_2[2:0] rx_alt_serdes_clk[2] O For 200GE/400GE, these are the rx_am_sf degrade bits from the AM.

This signal is updated within 10 clock cycles after rx_flex_amflag_2 is pulsed.

rx_fec_am_sf_4[2:0] rx_alt_serdes_clk[4] O For 200GE/400GE, these are the rx_am_sf degrade bits from the AM.

This signal is updated within 10 clocks after rx_flex_amflag_4 is pulsed.

rx_lane_aligner_fill_valid s_axi_aclk O Validates the lane_aligner information relay.
rx_lane_aligner_fill_start s_axi_aclk O Indicates the start of the lane_aligner information burst.
rx_lane_aligner_fill[6:0] s_axi_aclk O Fill level indication. 1
  1. The rx_lane_aligner_fill signals are used to compute lane skew in various FEC modes (including NOFEC) for PTP purposes. From a PTP perspective, the aligner fill levels give an indication of the skew between the lanes. You can use this information to determine the best and worst case lane skew to lane 0, which is the reference lane for PTP.