Almost Full - 3.0 English - PG369

In this Coupled MAC+PCS mode, the AXI4-Stream interface provides an additional output: tx_axis_taf_N (where N corresponds to the client port number). The tx_axis_taf_N output is an "almost full" indication that is provided to ease AXI timing in applications where instantaneous tready deassertion might be difficult to accommodate. This taf signal is asserted at least one cycle ahead of tready deassertion. If the AXI (client input) and core (line drain) data rates are comparable, the interval between taf assertion and tready deassertion might be greater.

Furthermore, if the client deasserts tvalid, it might be that tready can never be asserted. Regardless of whether the taf signal is used or ignored by the user logic, deassertion of tready still causes an immediate bus stall in the cycle in which it occurs: no data presented on the AXI bus is consumed until tready is reasserted.

The general principle of the taf signal is that it indicates a bandwidth excess on behalf of the TX client driving the AXI bus. When taf is asserted, the client must lower its input data rate until taf is removed. The simplest approach is to halt the data flow and deassert tvalid on the cycle after taf is asserted. When the taf signal is not asserted, or starting the cycle after a falling edge of the taf signal, tvalid must be asserted for all back-to-back cycles from the start of a frame until it completes.

Figure 1. AXI4-Stream Transmit taf Behavior

In some scenarios, the use of taf might cause the DCMAC Subsystem to insert a small, but measurable amount of unnecessary IDLE between TX frames. This extra IDLE can be avoided in one of two ways:

1. Increase the frequency of tx_axi_clk by 3.5% above nominal for 100GE/200GE, or 10% above nominal for 400GE.
2. Configure the AXIS_TAF_BP_THRESH setting (see the CONFIGURATION_EMPTY7 register in the dcmac-reg-map document) to 0x3F.