RS-FEC Statistics TDM Ports - 2.5 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2025-02-12
Version
2.5 English

Statistics related to the RS-FEC are captured on the RS-FEC statistics time division multiplexed (TDM) interface.

Note: Signals in the preceding table are clocked by the rx_axi_clk.
Table 1. RS-FEC Statistics TDM Port Descriptions: RX Direction
Port Name I/O Description
rx_rsfec_tdm_stats_data[15:0] O TDM data
rx_rsfec_tdm_stats_start O Indicates the start of a new TDM cycle.
rx_rsfec_tdm_stats_valid O Validates rx_rsfec_tdm_stats_start and rx_rsfec_tdm_stats_data.
c<n>_stat_rx_corrected_lane_delay*[15:0] I/O: O FEC lane delay value 1
c<n>_stat_rx_corrected_lane_delay_valid I/O: O FEC lane delay value valid
  1. The FEC lane delay values can be calculated from a combination of the information from the rx_lane_aligner_fill[6:0] TDM output port and the stat_rx_fec_delay_* information from the stats TDM interface. Specifically: real_lane_delay[lane] = (aligner_fill[lane] – 2) * 40 + (lane_delay[lane] % 40)

A complete description of the statistics map and the individual statistics can be found in the Register Space section.

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