Using Floating-Point in the AI Engine - 2024.1 English

Introduction

The purpose of this set of examples is to understand floating-point vector computations within the AI Engine.

IMPORTANT: Before beginning the tutorial, make sure that you have installed the Vitis software. The AMD Vitis™ release includes all the embedded base platforms including the VCK190 base platform that is used in this tutorial. In addition, ensure that you have downloaded the Common Images for Embedded Vitis Platforms from [this link] (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html). The ‘common image’ package contains a prebuilt Linux kernel and root file system that can be used with the Versal board for embedded design development using Vitis. Before starting this tutorial, run the following steps:

1. Go to the directory where you have unzipped the Versal Common Image package.

2. In a Bash shell, run the /Common Images Dir/xilinx-versal-common-v2024.1/environment-setup-cortexa72-cortexa53-xilinx-linux script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, run the /Common Images Dir/xilinx-versal-common-v2024.1/sdk.sh.

3. Set up your ROOTFS, and IMAGE to point to the rootfs.ext4 and Image files located in the /Common Images Dir/xilinx-versal-common-v2024.1 directory.

4. Set up your PLATFORM_REPO_PATHS environment variable to $XILINX_VITIS/lin64/Vitis/2024.1/base_platforms/. This tutorial targets the VCK190 production board for 2024.1 version.

AI Engine Architecture Details

Versal™ adaptive SoCs combine programmable logic (PL), processing system (PS), and AI Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. A host of tools, software, libraries, IP, middleware, and frameworks enable Versal adaptive SoCs to support all industry-standard design flows.

AI Engine array

As seen in the image above, each AI Engine is connected to four memory modules on the four cardinal directions. The AI Engine and memory modules are both connected to the AXI-Stream interconnect.

The AI Engine is a VLIW (7-way) processor that contains:

• Instruction Fetch and Decode Unit

• A Scalar Unit

• A Vector Unit (SIMD)

• Three Address Generator Units

• Memory and Stream Interface

AI Engine Module

Have a look at the fixed-point unit pipeline, as well as floating-point unit pipeline within the vector unit.