Generating AIE Wrapper Stub Module - 2023.2 English

The AIE wrapper stubs will be generated based on the external PLIO declarations in the ADF graph. You need to follow below steps for generating these stubs for the AIE.

1. Perform the ADF graph compilation to generate scsim_config.json file that resides in Work/config/scsim_config.json directory. This config file contains information on the PLIOs declared in the graph.

   v++ -c --mode aie --platform=$(PLATFORM) --aie.pl-freq 500 --aie.adf-api-log-level 3 --include=./aie  --output=graph.json aie/graph.cpp
   

   or

   make compile PLATFORM=$PLATFORM_REPO_PATHS/xilinx_vck190_base_202310_1/xilinx_vck190_base_202310_1.xpfm
   

2. Using this config file as argument to the gen_aie_wrapper.py script, you can autogenerate Verilog stub modules based on ext PLIO declared in ADF Graph.

   python3 ${XILINX_VITIS}/data/emulation/scripts/gen_aie_wrapper.py -json Work/config/scsim_config.json --mode <wrapper/vivado> 
   

• Tip: The python script is available in the Vitis install area as mentioned in above path. There are two modes for the script i.e., wrapper and vivado mode. By default, the script runs in Vivado mode. If run with wrapper mode, it only generates aie_wrapper_ext_tb.v.

• For x86simulation, you will have to manually write this wrapper as scsim_config.json is not available for x86sim flow.

The name of the instance stubs must be identical to the name of the corresponding external PLIOs in graph.h (“in_classifier” and “out_interpolator” as mentioned below), and these name of the instances in graph.h will be reflected in the generated aie_wrapper_ext_tb.v file.

pl_in0 = adf::input_plio::create("in_classifier",adf::plio_32_bits);
out0 = adf::output_plio::create("out_interpolator",adf::plio_32_bits);

After step 2, you can see aie_wrapper_ext_tb.v is generated that has instances of sim_ipc_axis modules that can be directly instantiated in your external testbench.