Step 3 - Interfacing ADF graph to Programmable Logic - 2023.2 English

Vitis Tutorials: AI Engine (XD100)

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2023.2 English

To set up the ADF graph to interface with the polar_clip RTL kernel and the mm2s and s2mm HLS kernels, you must add connections to PLIOs that represent the respective PL kernels.

  1. The following graph.h shows how to connect to the RTL kernel.

      adf::source(interpolator) = "kernels/interpolators/";
      adf::source(classify)    = "kernels/classifiers/";
      //Input PLIO object that specifies the file containing input data
      in = adf::input_plio::create("DataIn1", adf::plio_32_bits,"data/input.txt");
      clip_out = adf::input_plio::create("clip_out", adf::plio_32_bits,"data/input2.txt");
      //Output PLIO object that specifies the file containing output data
      out = adf::output_plio::create("DataOut1",adf::plio_32_bits, "data/output.txt");
      clip_in = adf::output_plio::create("clip_in",adf::plio_32_bits, "data/output1.txt");
  2. Note the following:

    • Two additional PLIO objects clip_in and clip_out are added. These are to hook up to the polar_clip RTL kernel.

    • There are additional net objects to hook up the RTL kernel to the rest of the platform object.

For more information on RTL kernels in the AI Engine see: Design Flow Using RTL Programmable Logic.

  1. Compile the graph using the following command:

    v++ --mode aie -c  --target=hw --include="/include" --include="./aie" --include="./data" --include="./aie/kernels" --include="./"  --aie.workdir=./Work --platform=${XILINX_VITIS}/base_platforms/xilinx_vck190_base_202320_1/xilinx_vck190_base_202320_1.xpfm aie/graph.cpp


    make aie