Version: Vitis 2024.1
Super Sampling Rate FIR Filter
The purpose of this third part of the tutorial is to understand how to implement a FIR filter that has an input sample rate above the clock frequency of the AI Engine array.
Navigate to the SingleStreamSSR directory to continue.
Super Sampling Rate and Polyphase
When the input sampling Rate is above the clock frequency of the processor (Super Sampling Rate), samples must be acquired in parallel. For a 2.5 Gsps input sample rate, you can specify that the filter should receive two samples at a 1.25 GHz rate, which can be seen as two data streams (Polyphase decomposition), each one at 1.25 Gsps. Because the AI Engine array AXI-Stream network is limited to 1.25 GHz (VCK190 device speed grade), the high sampling rate input (above 1.25 Gsps) is to be decomposed into multiple phases to be processed.
As a first example, suppose there is a 2.5 Gsps data stream to be processed, it can be split into two phases to be routed to the AI Engine array:
A 6.26 Gsps data stream must be split into 5 phases: