Estimated time: 4 hours
make all
or
v++ -l \
-t hw \
--platform xilinx_vck190_base_202410_1 \
--save-temps \
-g \
--optimize 2 \
--hls.jobs 8 \
--config ./conn.cfg \
--clock.defaultFreqHz 150000000 \
--temp_dir ./build/_x_temp.hw.xilinx_vck190_base_202410_1 \
--report_dir ./build/reports/_build.hw.xilinx_vck190_base_202410_1/hpc \
--advanced.param compiler.userPostSysLinkOverlayTcl=./post_sys_link.tcl \
-o './build/build_dir.hw.xilinx_vck190_base_202410_1/hpc.xclbin' \
../Module_03_pl_kernels/build/_x_temp.hw.xilinx_vck190_base_202410_1/packet_sender.xo \
../Module_03_pl_kernels/build/_x_temp.hw.xilinx_vck190_base_202410_1/mm2s_mp.xo \
../Module_03_pl_kernels/build/_x_temp.hw.xilinx_vck190_base_202410_1/packet_receiver.xo \
../Module_03_pl_kernels/build/_x_temp.hw.xilinx_vck190_base_202410_1/s2mm_mp.xo \
../Module_02_aie/build/libadf.a
Full System Design
The AMD Vitis Linker (v++ -l
) is used to link multiple kernel objects (XO), together with the hardware platform XSA file, to produce the device binary XCLBIN file.
Review the conn.cfg
file. It creates an instance of each PL kernel described previously and provides the connection scheme between them and the AI Engine graph. At the end of the file, there are Vivado™ tool options specified to close timing and run the design at 300 MHz.
Design Implementation
The following image was taken from the Vivado project for the entire design. It depicts the hardware implementation determined by the place-and-route on the adaptive SoC device.
References
Next Steps
After linking the AI Engine design with the PL datamovers, you are ready to create the host software in the next module, Module 05 - Host Software.
Support
GitHub issues will be used for tracking requests and bugs. For questions go to support.xilinx.com.
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