Custom Base Platform Creation - 2024.1 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2024-10-30
Version
2024.1 English

Platforms

A platform is the starting point of your design and will be used to build Vitis software platform applications.

NOTE: AMD recommends using the VCK190 base platform provided on xilinx.com as a starting point for designs. This page is intended for users who would like to understand how the base platform is generated. Other users can start directly from AI Engine Development.

In this first section of the tutorial, an example of how to create a new platform is shown. This starts with building the hardware system using the AI Engine in the AMD Vivado™ Design Suite.

This is in most ways a traditional AMD Vivado™ design. You are building the platform, that is, the part of the design that you do not want the Vitis tools to configure or modify. This can include completely unrelated logic, any hierarchy you want to have in the design, but there are some rules that you must follow:

  • Your design must contain an IP integrator block diagram containing the CIPS, NOC, and other infrastructure IP.

  • Your design must have at least one clock that you will expose to Vitis for use with any kernels that it adds. This clock must have an associated proc_sys_reset block.

This tutorial targets the VCK190 board (see https://www.xilinx.com/products/boards-and-kits/vck190.html).

Step 1: Build the AMD Versal™ Extensible Embedded Platform Example Design in Vivado

  1. Launch Vivado IDE, and select Open Example Project from the Welcome window. You can also do it by clicking File from the menu, and select Project and then Open Example.

  2. Click Next to skip the first page of the wizard. In the template selection page, select the Versal Extensible Embedded Platform template. Click Next.

  3. Name this project as custom_pfm_vck190 and click Next.

  4. In the board selection page, select VCK190 Evaluation Platform. If you are going to target other platform, you can select others. Click Next.

  5. In the design preset page, keep the default settings. Note that the AI Engine is enabled:

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  6. Click Finish to complete the example design creation phase, and this will open up the Vivado project with the template design you just created. You can open the block design to view the details of the platform design. By using the pre-built template, you can easily get a validated hardware design of the platform to move on to the next step. In your real design development procedure, you can use this as a baseline design and make further modifications on top of it.

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  7. Click Generate Block Design from the Flow Navigator panel on the left, click Generate, and wait for the process to complete.

NOTE: A critical warning is displayed by Vivado when generating the Block Design. This is due to the fact that the Interrupt Controller IP has an unconnected input. This can be ignored as this input will be connected automatically by Vitis later in the flow.

  1. Click File from the menu, and select Export > Export Platform.

    a. On the second page, select Hardware and hardware emulation as the platform type.

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    b. On the third page select Pre-synthesis.

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    c. On the fourth page, add the name of the platform.

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    d. On the fourth page, set the name of the XSA, and click Finish.

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  2. Close the Vivado project after platform export process finishes.

Note: The vivado platform creation can be automated by running “make vivado_platform”

Step 2: Build the Platform in the Vitis Software Platform

  1. Open the Vitis Unified IDE, and select a workspace.

  2. On the Welcome Page, select Create Platform Component, or select File → New Component → Platform.

  3. Set the platform component name to base_pfm_vck190 and click Next.

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  4. Select Hardware Design and use the XSA generated during the previous step and click Next

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  5. Set the Operating System to aie_runtime and the Processor to ai_engine and click Next. Then click Finish to create the platform component.

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  6. Then build the platform by clicking on Build In the flow navigator with the base_pfm_vck190 component selected.