Section 5: Simulate the AI Engine Graph using the aiesimulator and Viewing Trace and Profile Results in Vitis Analyzer - 2023.2 English

Vitis Tutorials: AI Engine (XD100)

Document ID
XD100
Release Date
2024-03-05
Version
2023.2 English

After the graph has been compiled, you can simulate your design with the aiesimulator command. This uses a cycle-approximate model to test your graph and get preliminary throughput information early in the design cycle, while the PL developers continue to work on the platform for the application.

Note: Simulating the design with VCD will increase simulation runtime. To learn more about this feature, see AI Engine SystemC Simulator.

  1. To run simulation use the command:

    make sim TARGET=hw
    

    or

    aiesimulator --profile --dump-vcd=tutorial --pkg-dir=./Work
    
| Flag | Description |
| ---- | ----------- |
| --profile | Profiles all kernels, or select kernels (col,row)...(col,row).|
| --dump-vcd | Grabs internal signals of tiles and dumps it in a VCD file. |
| --pkg-dir | The ***Work*** directory. |
  1. When simulation has completed, use a terminal to navigate to the aiesimulator_output directory by running: cd aiesimulator_output; ls

    You should see something similar to this:

    
    

aiesim_options.txt memconfig.json profile_funct_18_1.txt profile_funct_19_0.xml profile_instr_18_0.txt profile_instr_18_1.xml profile_instr_19_1.txt data profile_funct_18_0.txt profile_funct_18_1.xml profile_funct_19_1.txt profile_instr_18_0.xml profile_instr_19_0.txt profile_instr_19_1.xml default.aierun_summary profile_funct_18_0.xml profile_funct_19_0.txt profile_funct_19_1.xml profile_instr_18_1.txt profile_instr_19_0.xml ```

The files prefixed with `profile_` are the outputs of the profiling and calculated per tile. In this tutorial, profiling is done for all tiles that are used, but you can limit profiling to specific tiles by providing the row and column of the tile. For more information about profiling with `aiesimulator` see [here](https://www.xilinx.com/html_docs/xilinx2021.2/vitis_doc/simulate_graph_application.html#yfx1512608800495). You can open up these files to see what was calculated, but it is better to view it in Vitis Analyzer where it is curated. The `data` directory is generated here with the output file(s) you have in the `graph.cpp` for the PLIO objects. Finally, the `default.aierun_summary` is generated, which contains all the information generated by `aiesimulator` with profiling and trace information. Opening this file in Vitis Analyzer allows you to browse all the output files, and profile/trace data.

**NOTE**: The `tutorial.vcd` is generated on the same level as the `./Work` directory.

You can now open the generated `default.aierun_summary` from the `aiesimulator_output` directory for Vitis Analyzer.
  1. To do this,run the command:

    vitis_analyzer ./aiesimulator_output/default.aierun_summary
    

    With this tool you can use a variety of views to debug and potentially optimize your graph.

    The Summary view provides an overview of running aiesimulator. As you can see in the following figure, it provides information on status, version used, time, platform used, and the command line used to execute.

    Vitis Analyzer Summary

  2. Click Profile.

    The Profile View provides detailed information collected during the simulation. Information includes cycle count, total instructions executed, program memory, and specific information per functions in the two tiles that the kernels are programmed.

    Vitis Analyzer Profile

    This is the top-level view of the profile. The left column allows you to select one of many types of reports generated per function.

  3. Select the first Total Function Time from this column. You will see the following.

    Vitis Analyzer Profile 1 Kernel

    In this chart you can see what function is called most, function time, etc. This information can be useful in determining if the tile is under- or over-utilized in your design.

  4. Click Graph.

    The Graph view provides an overview of your graph and how the graph is designed in a logical fashion. In this view, you can see all the PLIO ports, kernels, buffers, and net connections for the entire ADF Graph.

    Note: This view, as well as the Array view have cross-probe selection, meaning selecting an object in this view will select it in the other and vice versa.