Section 1: Overview of the Design that Will be Used in this Tutorial - 2023.2 English

Vitis Tutorials: AI Engine (XD100)

Document ID
XD100
Release Date
2024-03-05
Version
2023.2 English

The following figure gives an overview of how the data will flow through this example design.

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The following table gives a brief overview of all the functionalities involved.

Name Type Functionality
Interpolator AIE Kernel Interpolate using two samples by taking in 128 cint16 samples block as input and producing 256 cint16 samples block as an output.
Polar Clip User RTL Performs threshold detection and clipping.
Classifier AIE Kernel Does some simple classification as per complex plane and produces plane numbers (from 0 to 3) based on the complex value.

There are two AIE kernels communicating with the user RTL block. The AIE kernels have four PLIOs, two being file I/Os i.e., in_interpolator and out_classifier and the other two being external I/Os i.e., out_interpolator and in_classifier responsible for propagating traffic in/out of the AIE kernels from the external process running the user RTL block.