Lab 2: Vitis Makefile Flow

Initialization

All labs rely on a set of source files that are available in the Files sub-directory:

AIE contains the source files for the AI Engine application.
AIE2 contains the source files for the AI Engine application with location constraints for one of the AI Engine kernels.
Constraints contains the PLIO constraints file for the second phase.
data contains data files used to verify application functionality.
HwLink contains a system configuration file to link AI Engine and PL kernels.
PL contains all PL kernels (mm2s, s2mm, and polar_clip).
PS contains the host (A72) application that runs the PL kernels, launches the graph, and verifies the output.

Go to the lab directory:

cd WithIntermediatePlatform

Phase 1: Creating a Fixed Platform from an AI Engine Application and PL Kernels

This lab uses the same files as the AMD Vitis™ IDE flow, but all the operations are completed within a terminal.

To complete phase 1, change directory: cd Phase1.

This directory contains a single file, which is a Makefile. Open it in any editor or display it in the terminal using more, less, or cat. The Makefile contains three stages:
- kernels: To build the PL kernels. The output is a number of XO files, which are packaged RTL kernels.
- aie: To build the AI Engine graph. The output is the file libadf.a, which is the compiled graph with all the PL/AI Engine interfaces.
- link: To link the AI Engine array design with the PL design. This stage creates the XCLBIN and the XSA files.

There are also optional stages to simulate the AI Engine application using the aiesim target and run_emu to launch hardware emulation that includes all the PL kernels.

In the terminal, type make clean phase1 and all the required stages (kernels, aie, and link) will be run in the terminal as well as hardware emulation (package and run_emu).

Check the placement of the AI Engine kernels using Vitis Analyzer and opening the graph.aiecompile_summary file.

Note: The hardware emulation does not launch automatically. You have to launch it manually:

cd /run/media/mmcblk0p1
./host.exe a.xclbin

At the end of the simulation the following message is displayed:

mm2s (DataIn1) completed with status(4)
[59672.228524] zocl-drm axi:zyxclmm_drm:  ffff0008003cd410 kds_del_context: Client pid(2424) del context CU(0x1)
polar_clip completed with status(4)
[59672.230697] zocl-drm axi:zyxclmm_drm:  ffff0008003cd410 kds_del_context: Client pid(2424) del context CU(0x2)
s2mm (DataOut1) completed with status(4)
[59674.351664] zocl-drm axi:zyxclmm_drm:  ffff0008003cd410 kds_del_context: Client pid(2424) del context CU(0xffffffff)
[59674.353188] zocl-drm axi:zyxclmm_drm:  ffff0008003cd410 kds_del_context: Client pid(2424) del context CU(0x0)
TEST PASSED
Releasing remaining XRT objects...
[59674.355157] [drm] bitstream 8ae06494-3226-bda4-94c7-906e136725ad unlocked, ref=0
[59674.452197] zocl-drm axi:zyxclmm_drm: zocl_destroy_client: client exits pid(2424)
root@versal-rootfs-common-20232:/run/media/mmcblk0p1#

You can get out of QEMU by hitting Ctrl + a x.

Phase 2: Using a Platform Generated by Vitis and Modifying the AI Engine Application

Phase 2 contains the following stages:

aie2: As in the previous phase, this stage builds an AI Engine application, but in this case, it uses the new platform constraints.
host: Compile the PS application.
package2: Create the PDI to load onto the device (hw_emu).
run_emu: Launch the simulation and verifies that the output is still correct.

The new platform is named Phase1_container. It has been created by the vitis --link stage during Phase1. The .xsa file contains all the constraints corresponding to the interface and is located in the directory Phase1:

# New platform
PFM := Phase1_container
# Phase 1 output
XCLBIN := ../Phase1/$(PFM).xclbin
XSA    := ../Phase1/$(PFM).xsa

The first stage, make aie2, consists of generating the AI Engine application graph using the previously created .xsa file. The kernel itself has not changed but a kernel location constraint has been added to the graph so that you can see a big difference in the kernel placement. Check this new placement using Vitis Analyzer on the compile summary.

The second stage, make host, is straightforward and you can see that the first object file that is created is aie_control_xrt.o. It is built from the CPP file that has been generated by the second stage.

The third stage, make package2, has various outputs. Among them is a file named launch_hw_emu.sh, which is used to run the hardware emulation in the last stage.

The fourth and final stage, make run_emu, starts the hardware emulation that also verifies the correctness of the output.

Perform On-Board Testing

To perform an on-board testing, the same stages can be replicated but with a different target:

For phase 1, type make TARGET=hw clean phase1.
For phase 2, type make TARGET=hw phase2.

When the phase 2 process is finished, an sd_card.img file has been created and can be used as in the Direct Recompile Makefile flow.
To launch the program on the board, type the following command:

cd /run/media/mmcblk0p1
./host.exe a.xclbin

Support

GitHub issues will be used for tracking requests and bugs. For questions go to forums.xilinx.com.

License

The MIT License (MIT)

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.