Scatter Gather Mode (C_INCLUDE_SG = 1) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

New descriptor fields are added to support multichannel and 2-D transfers. As described in AXI DMA Multichannel Operation, AXI DMA supports efficient two-dimensional memory access patterns, transferring 2-D blocks across the AXI4-Stream channel. Memory access patterns are controlled with three parameters: HSIZE, VSIZE, and STRIDE. Multiple descriptors per packet are supported through the Start of Packet and End of Packet flags.

In this mode, the AMD Vivado™ Integrated Design Environment (IDE) IP customization feature disables the Status/Control Stream.

AXI DMA can be set in multichannel mode by enabling the Multi Channel Mode and selecting the required number of channels on MM2S and S2MM paths.