MM2S_SA_MSB (MM2S DMA Source Address Register – Offset 1Ch) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the upper 32 bits of the Source Address for reading system memory for the Memory Map to Stream DMA transfer. This is applicable only when the DMA is configured for an address space greater than 32.

Figure 1. MM2S_SA_MSB Register

Table 1. MM2S_SA_MSB Register Details
Bits Field Name Default Type Access Type Description
31 to 0 Source Address zeros R/W Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.