MM2S_STATUS (MM2S Status) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This value provides status for MM2S transfers from memory map to stream.

Figure 1. MM2S_STATUS

Table 1. MM2S_STATUS Details
Bits Field Name Description
25 to 0 Transferred Bytes

Indicates the size in bytes of the actual data transferred for this descriptor. This value indicates the amount of bytes to transmit out on MM2S stream. This value should match the Control Buffer Length field.

The usable width of Transferred Bytes is specified by the parameter, Width of Buffer Length Register. A maximum of 67,108,863 bytes of transfer can be described by this field. AXI_DMA does not update these fields when configured in Micro mode.

Note: Setting the Buffer length Register Width smaller than 26 reduces FPGA resource utilization. This field is not updated when AXI_DMA is configured in Micro mode.
27 to 26 Reserved These bits are reserved and should be set to zero.
28 DMAIntErr

DMA Internal Error. Internal Error detected by primary AXI Data Mover. This error can occur if a 0 length bytes to transfer is fed to the AXI Data Mover. This only happens if the buffer length specified in the fetched descriptor is set to 0.

This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.

  • 0 = No DMA Internal Errors.
  • 1 = DMA Internal Error detected. DMA Engine halts.
29 DMASlvErr

DMA Slave Error. Slave Error detected by primary AXI Data Mover. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.

  • 0 = No DMA Slave Errors.
  • 1 = DMA Slave Error detected. DMA Engine halts.
30 DMADecErr DMA Decode Error. Decode Error detected by primary AXI Data Mover. This error occurs if the Descriptor Buffer Address points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No DMA Decode Errors.
  • 1 = DMA Decode Error detected. DMA Engine halts.
31 Cmplt Completed. This indicates to the software that the DMA Engine has completed the transfer as described by the associated descriptor. The DMA Engine sets this bit to 1 when the transfer is completed. The software might manipulate any descriptor with the Completed bit set to 1.
  • 0 = Descriptor not completed.
  • 1 = Descriptor completed.
Note: If a descriptor is fetched with this bit set to 1, the descriptor is considered a stale descriptor. An SGIntErr is flagged, and the AXI DMA engine halts.