MM2S_CURDESC (MM2S DMA Current Descriptor Pointer Register - Offset 08h) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the Current Descriptor Pointer for the Memory Map to Stream DMA Scatter Gather Descriptor Management.

Figure 1. MM2S CURDESC Register

Table 1. MM2S_CURDESC Register Details
Bits Field Name Default Value Access Type Description
5 to 0

(Offset 0x38)

Reserved 0 RO Writing to these bits has no effect and they are always read as zeros.
31 to 6 Current Descriptor Pointer zeros R/W

(RO)

Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.

When the DMA Engine is running (DMACR.RS=1),CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.

On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.

Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.