S2MM_DMASR (S2MM DMA Status Register – Offset 34h) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)
Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the status for the Stream to Memory Map DMA Channel.

Figure 1. S2MM DMASR Register

Table 1. S2MM DMASR Register Details
Bits Field Name Default Value Access Type Description
0 Halted 1 RO DMA Channel Halted. Indicates the run/stop state of the DMA channel.
  • 0 = DMA channel running.
  • 1 = DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1.
Note: When halted (RS= 0 and Halted = 1), writing to TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
1 Idle 0 RO DMA Channel Idle. Indicates the state of AXI DMA operations. For Scatter /Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.

For Direct Register Mode when IDLE indicates the current transfer has completed.

  • 0 = Not Idle.
  • 1 = Idle.
Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA is configured for Direct Register Mode.
2 Reserved 0 RO Writing to this bit has no effect and it is always read as zero.
3 SGIncld C_ INCLUDE_ SG RO Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
4 DMAIntErr 0 RO DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.

This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shutdown, the DMASR.Halted bit is set to 1.

  • 0 = No DMA Internal Errors
  • 1 = DMA Internal Error detected.
5 DMASlvErr 0 RO DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0 and when the engine has completely shut down the DMASR.Halted bit is set to 1.
  • 0 = No DMA Slave Errors
  • 1 = DMA Slave Error detected.
6 DMADecErr 0 RO DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No DMA Decode Errors
  • 1 = DMA Decode Error detected.
7 Reserved 0 RO Writing to this bit has no effect and it is always read as zero.
8 SGIntErr 0 RO Scatter Gather Internal Error. This error occurs if a descriptor with the Complete bit already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Internal Errors
  • 1 = SG Internal Error detected.

This error cannot be logged into the descriptor.

Note: Applicable only when Scatter Gather is enabled
9 SGSlvErr 0 RO Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to gracefully halt. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Slave Errors
  • 1 = SG Slave Error detected. DMA Engine halts.

This error cannot be logged into the descriptor.

Note: Applicable only when Scatter Gather is enabled.
10 SGDecErr 0 RO Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR point to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0 and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Decode Errors
  • 1 = SG Decode Error detected. DMA Engine halts.

This error cannot be logged into the descriptor.

Note: Applicable only when Scatter Gather is enabled.
11 Reserved 0 RO Writing to this bit has no effect and it is always read as zeros.
12 IOC_Irq 0 R/WC Interrupt on Complete. When set to 1 for Scatter/Gather Mode indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode indicates an interrupt event was generate on completion of a transfer.

If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.

  • 0 = No IOC Interrupt
  • 1 = IOC Interrupt detected.

Writing a 1 to this bit clears it.
13 Dly_Irq 0 R/WC Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer timeout. If the corresponding bit in S2MM_DMACR is enabled (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.
  • 0 = No Delay Interrupt
  • 1 = Delay Interrupt detected.

Writing a 1 to this bit clears it.

Note: Applicable only when Scatter Gather is enabled.
14 Err_Irq 0 R/WC Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit in S2MM_DMACR is enabled (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.

Writing a 1 to this bit clears it.

  • 0 = No Error Interrupt
  • 1 = Error Interrupt detected.
15 Reserved 0 RO Writing to this bit has no effect and it is always read as zeros.
23 to 16 IRQThresholdSts 01h RO Interrupt Threshold Status. Indicates current interrupt threshold value. The value programmed in the IRQThreshold field in S2MM_CR is decremented on every packet transfer and reflected here. Before the DMA is started or before receiving the first packet, this register will have the same value as programmed in the IRQThreshold field of S2MM_CR.
Note: Applicable only when Scatter Gather is enabled.
31 to 24 IRQDelaySts 00h RO Interrupt delay time Status. Indicates current interrupt delay time value.
Note: Applicable only when Scatter Gather is enabled.